FPGA1394 V3 board
Robot / hardware buildZynq XC7Z020-based robot control interface board design reference with dual Ethernet and Altium sources. [1] [2] [5] [6]
Build & first use →Official websiteUpstream build guide
- Cost
- No current cost or bill of materials established yet.
- Source rights
- Some licenses are unresolved. Review licenses
- Unknowns
- host computer, tools, operating system not fully established. Review gaps
Source researched · Not tested by us
Sources checked · Research details
Licenses & related hardware
- License
- not fully assessed for electronics, documentation · Details by part
Overview
FPGA1394 V3 provides Altium hardware-design sources for a robot-control interface board based on the Xilinx Zynq XC7Z020 system-on-chip. Its README distinguishes this FPGA/dual-core ARM design from the earlier Spartan-6 boards and identifies two Ethernet ports. This entry covers the board design reference, not supplied FPGA logic, a complete controller or a tested communication system. [1]
No project license declaration was established by the inspected README/project-file excerpts and the pinned tree's license-filename scan. This was not an exhaustive content audit of every source file. The files are publicly accessible for inspection, but unrestricted manufacturing, modification or redistribution rights are not inferred. Separate Zynq tools, firmware and bought-in component terms also require review. [1] [2] [7]
Is this for you?
- Known limitations
- No project reuse grant identified in inspected README/tree; unlicensed source visibility only.
- V3 Zynq differs from V1/V2 Spartan 6; V3.0 prototype files not released per README.
- Selected Altium streams/sheet records inspected, not full net reconstruction/native DRC/manufacturing/runtime proof.
Editorial assessment of bounded source evidence; no runtime, fit, manufacturing or compatibility proof.
What you need
Hardware & parts
Assembly & first use
Open the upstream getting-started guide [1] [2] [5] [6]
- Choose V3.1 or V3.2 configuration and match release changes/BOM.
- Inspect actual PCB and schematic parameter records; check separate firmware/host dependencies.
- Resolve permissions and complete fabrication/assembly/electrical requirements before manufacture.
Editorial assessment of bounded source evidence; no runtime, fit, manufacturing or compatibility proof.
Cost
No current, complete configuration-specific build cost has been established for this profile.
3D preview
Preview not available yet. No hosted preview has been prepared for the configuration described in this profile. Inspect the linked sources and their reuse terms; a manufacturing-ready assembly has not been established by this preview status.
Model sources
No hosted preview has been prepared for the configuration described in this profile. Inspect the linked sources and their reuse terms; a manufacturing-ready assembly has not been established by this preview status.
Project notes
Verify that the actual design source is present
The original S01.SchDoc and FPGA3.PcbDoc were fetched at the reviewed revision and matched to their Git identities. Compound-file inspection found schematic parameter records and numerous PCB source streams. These are actual structured Altium artifacts, beyond the project manifest and photographs. The inspection does not establish a successful native Altium load, complete schematic/net reconstruction, resolved libraries or a passing board design-rule check. [5] [6]
The README identifies the remaining schematic sheets, a BOM workbook and a Panel directory with fabrication/assembly material. Those are concrete sources to inspect next; this bounded review did not inspect every sheet or validate a complete manufacturing package. Do not equate one decoded schematic sheet with the full board's verified circuitry. [1]
Choose the V3 configuration before matching components
The README says revision 3.0 was a prototype whose design files were not released, revision 3.1 was the initial release, and revision 3.2 made additional changes. V3.2 removes specified zero-ohm links for an Ethernet PHY converter, adds supply soft-start capacitors and test points, and changes paste-mask openings. Those details matter when matching assembly files and components rather than treating all V3 boards as identical. [1]
The previous V1/V2 design repository is a related source, not another name for this Zynq design. Its Spartan-6 assumptions, firmware and port configuration cannot be transferred solely because the project family is shared. Identify the selected V3 BOM, board, host link and separate FPGA/ARM firmware before attempting system integration. No such firmware pairing or host session was reproduced here. [1]
A bounded next investigation
Begin with the intended V3.1/V3.2 configuration and its actual board/schematic files, then reconcile the referenced BOM and panel assembly sources. Resolve permissions before fabrication or redistribution. This review did not establish a current complete delivered cost, component stock, native design validity, power sequencing, FPGA programming, Ethernet operation or timing performance. Container and source-record checks support an honest design-reference entry; they do not prove a working robot controller. [1] [5] [6]
What we checked
Pinned source and selected artifact structure review only; no dependency installation, upstream build, native CAD/kernel/fit/strength validation, fabrication, wiring, calibration, simulation, powered operation or performance testing. Original archives stay private.
Not yet established
- Requirements: operating system, host computer, tools
Updates
- Upstream last updated
- Not established
- Latest release
- Not established
- Profile updated
- Nov 1, 2026
- Sources last checked
- Nov 1, 2026
- Next review
- Dec 1, 2026
- Reviewed revision
e0eb132
Source files and licenses
Distinct inspectable robotics design reference with bounded initial inspection route; limitations/rights explicit.
| Layer | Availability / license |
|---|---|
| electronics | available · License not fully assessed Unlicenseddesignreference;actualAltiumCFBsource container inspected. [6] |
| documentation | available · License not fully assessed No licensegrantidentified. [1] |
Outside the selected contribution; no separate released layer claimed.
References
Each source links to the exact revision we read. “Used for” shows where this page relies on it.
- S001 README.md
Revision, date & where cited
jhu-cisst/FPGA1394V3 contributors · github.com · revision
e0eb132· README.md at · Accessed Nov 1, 2026
Used for: Overview, Is this for you?, What you need, Hardware & parts and 5 more - S002 FPGA3.PrjPCB
Revision, date & where cited
jhu-cisst/FPGA1394V3 contributors · github.com · revision
e0eb132· FPGA3.PrjPCB at · Accessed Nov 1, 2026
Used for: Overview, Is this for you?, What you need, Hardware & parts and 1 more - S003 S01.SchDoc
Revision, date & where cited
jhu-cisst/FPGA1394V3 contributors · github.com · revision
e0eb132· S01.SchDoc at · Accessed Nov 1, 2026 - S004 FPGA3.PcbDoc
Revision, date & where cited
jhu-cisst/FPGA1394V3 contributors · github.com · revision
e0eb132· FPGA3.PcbDoc at · Accessed Nov 1, 2026 - S005 S01.SchDoc
Revision, date & where cited
jhu-cisst/FPGA1394V3 contributors · github.com · revision
e0eb132· S01.SchDoc at · Accessed Nov 1, 2026
Used for: Is this for you?, What you need, Hardware & parts, Assembly & first use and 2 more - S006 FPGA3.PcbDoc
Revision, date & where cited
jhu-cisst/FPGA1394V3 contributors · github.com · revision
e0eb132· FPGA3.PcbDoc at · Accessed Nov 1, 2026
Used for: Is this for you?, What you need, Hardware & parts, Assembly & first use and 3 more - S007 Pinned tree and bounded license inspection
Rootpaths and license-filename scope retained; no comprehensivegrant established.Revision, date & where cited
jhu-cisst contributors; filenameinspection byCodex · github.com · revision
e0eb132· Accessed Nov 1, 2026
Used for: Overview, Is this for you?
Correction guidance · Discussion is not enabled · Profile format 0.7.0-draft.5